An overview of the MOSFET device and some considerations on power handling
First and foremost, please allow me to explain the MOSFET acronym as a two-section word: MOS and FET. Chaotically, let’s start with “FET”.
The “FET” section of the MOSFET acronym stands for Field Effect Transistor. A FET is basically an electronic device in which its output current is modulated by the voltage applied between the gate and source terminals. In an electronics point of view, this device is a voltage controlled current source which can either behaves as a switch (blocking or conducting current) or as an amplifier (amplifying signals).
Sequentially, the “MOS” in MOSFET means Metal-Oxide-Semiconductor. This acronym section implies on how the FET is constructed: the gate terminal of this device is connected to a METAL (aluminum, for example), which is placed over an OXIDE (Silicon Oxide, for example) sheet, which, in its turn, is placed over the SEMICONDUCTOR substrate. This type of device is represented in Figure 1.
The current that a n type MOSFET controls flows from the drain to the source (ID) terminals of the device. The region which the current flows is called “channel”. A wider channel means that more current may flow through the terminals while a narrower channel means that less current flows. The formation of such channel depends on the intensity of the voltage applied between the gate and source of the transistor and its size depends on the geometry of the transistor.
Note that this type of construction is called lateral (or planar) due to the current flowing laterally in the device. This is not *really* suited for power applications where high voltage and current are mandatory – there are other types of constructions, better suited for power handling, such as the vertical ones. To provide a deeper understanding of this situation, allow me to develop further:
The current of a planar MOSFET device operating in the saturation region is defined by the simplified expression:
Where W stands for the width and L for the length of the channel and K accounts for all other dependencies that affects the current of the transistor.
From equation (1), high currents are achieved by reducing L. Reducing L, however, decreases the maximum operating voltage of the device [1], limiting instantaneous voltage peaks.
So, how to achieve high power with voltage being limited by the employed process and material (silicon in the case of MOSFETs) and current being limited by geometry? Increasing W, adjusting polarization, selecting the optimum output impedance that allows highest power, and regarding the maximum voltage across (a method is explained in Annex 1 of [2]) all terminals of the device are some “sliders” we can move to optimize power handling capabilities.
Okay… but if lateral is not *really* suited for power applications, why using it instead of using other construction or technologies? Well, it so happens that this kind of construction is also used for logical and memory circuits, where thousands of MOSFETs are employed. By using such a standardized structure in applications such as in a power RF, costs and integration are optimized. Sure, it has drawn backs, but at some extent, it just works fine.
To be totally honest with you, we can also use some options available in the fabrication process in favor to achieve higher power capabilities at cost of using additional masks in the process of fabrication. Using these options are not something really huge to worry about, as foundries normally provide them characterized.
History time!
Both n and p channel MOSFETs were patented by Egyptian engineer Mohamed Atalla and by the Korean engineer Dawon Kahng in 1959 [3] at Bell Labs. In 1963 the Chinese American engineer Chih-Tang Sah and American Engineer Frank Wanlass combined both n and p complementary structures into a complementary MOS (CMOS) fabrication process at Fairchild Semiconductor [4].
Using cell options in a CMOS process to enhance power handling
To explain the usage of some fabrication options in favor of power handling, let’s start with the basic construction of a lateral MOSFET and literally, build upon it.
Thin Oxide FETs
A thin oxide FET is a MOSFET which the oxide between gate and substrate measures some dozens of Angstroms (well, that’s at least the case for both CMOS technologies I've worked with).This type of device is represented in Figure 1. Note this is not an accurate representation of a MOSFET device. A better representation is available at [1], chapter 1.7. Apart from that, this is the “standard” configuration for FET devices that are built upon a p substrate.
A thin oxide FET is suited for applications where speed is important: the thin insulator means lower oxide capacitance. However, speed performance costs a lower maximum voltage across terminals. This means that for a high amplitude voltage swing application, this isn’t the optimized choice. Just to example this situation: maximum voltage between terminals in a thin oxide device is about 1.5 V.
Thick Oxide FETs
A thick oxide FET, in its turn, is a MOSFET which its oxide between gate and substrate is thicker than a thin. For both technologies I’ve worked with, it measures at least two times the thin oxide’s thickness. This allows this type of device to withstand higher maximum voltage across terminals at the cost of lower speed. The maximum voltage between terminals of a thick oxide FET is about 2.5 V.
Triple Well FETs
Triple Well is a fabrication option that allows transistors to grow atop of a local substrate rather than being grown over the substrate bulk. This allows the transistor to be physically isolated from the bulk, reducing the induced voltages and currents from the bulk to the channel. This kind of transistor is especially interesting for LNAs where the noise figure matters. By using this option, NF can be instantly enhanced. Another advantage of using this type of option is that one might bias this local well with other voltage than that of the reference, allowing operating voltage to be clipped into a desired DC voltage – something really interesting for stacked MOSFETs architectures, for example.
An idea to use those options
An interesting way to take advantage of those options is by using them into a cascode amplifier architecture. In the cascode architecture, two transistors are stacked. The first one is a common-source (CS) while the second one is a common-gate (CG). The source terminal of the CG is connected to the drain of the CS. This architecture benefits from using thick oxide MOSFETs as voltage swings across MOSFETs may be higher than those of thin oxide MOSFETs. Apart from that, increasing W as needed increases the transcondutance gain of the transistors, allowing high IDs. Optimized voltage swing across terminals and high current is the combination of success for high power applications. Finally, using a triple well allows the voltage across the terminals to be referenced to the local well, instead of the bulk, allowing using a clipped DC voltage as reference.
*NOT SO* History time!
When building a p device, a n well is grown in the substrate. So a p device is actually made of a p substrate, a n well for the channel and p wells for drain and source. Processes that uses this type of construction are called “double-well”.
References
[1] The MOS transistor, by Yannis Tsivids and Colin McAndrew
[2] Amplificador de potência CMOS reconfigurável em potência e em banda de operação, by Fávero Santos (Qualification thesis) – unpublished.
[3] https://en.wikipedia.org/wiki/CMOS
[4] https://en.wikipedia.org/wiki/Field-effect_transistor#n-channel_FET
